A vertical NAND string device comprises a thin channel that has been formed along a pillar. Various devices, such as a select gate source (SGS), one or more non-volatile memory cells (NAND memory cells), one or more control gates and a select gate drain (SGD) are arranged along the thin channel. The channel is connected at one end to a bit line (BL) and at the other end to a source. A first select signal is applied to the SGD to control conduction through the channel at the BL end of the channel, and a second signal is applied to the SGS to control conduction through the channel at the source end of the channel. The vertical NAND string device can be arranged into a memory array in which the NAND memory cells are located at intersections of column signal lines (e.g., bit lines) and row signal lines (e.g., word lines). Individual column and/or row signal lines are electrically connected to a memory controller to selectively access and operate the NAND memory cells.
It will be appreciated that for simplicity and/or clarity of illustration, elements depicted in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. The scaling of the figures does not represent precise dimensions and/or dimensional ratios of the various elements depicted herein. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.